Digital Design Engineer

Posted 7 Days Ago
Be an Early Applicant
7 Locations
5-7 Years Experience
Information Technology • Manufacturing
The Role
Join the leading chiplet startup as a Digital Design Engineer. Define, implement, and ensure correctness of novel RTL for major blocks in chiplet based systems. Collaborate with cross-functional team to innovate high-volume, high-performance products. Responsibilities include RTL design, specification writing, formal verification, and silicon bring-up. Requires BS EE with 5 years of experience.
Summary Generated by Built In

Join the leading chiplet startup! As an Eliyan Digital Design Engineer, you will be working at a fast paced early stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be defining, implementing, and ensuring correctness of novel RTL for major blocks. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.

Key Responsibilities

  • As a digital design engineer, you will be involved in all phases of the design from concept brainstorm, architecture definition all the way to silicon bring-up and characterization
  • Writing detailed design specification based on product requirement
  • Providing high-quality RTL that meets the spec
  • Running formal tools and static checkers to guarantee RTL quality
  • Supporting design verification to ensure bug-free first silicon
  • Working with the physical design team to ensure timing closure and best PPA
  • Supporting silicon bring-up, performance and power characterization

Minimum Qualifications

  • Being flexible, team oriented, with a can-do attitude
  • RTL design using Verilog or SystemVerilog
  • Design of state machines, data/control paths, and clock domain crossing logic
  • Logic synthesis with proper timing constraints
  • Exposure to Design For Testing, understanding of scan concept and writing DFT friendly RTL
  • General knowledge of RTL simulation tools and related scripting languages
  • BS EE or equivalent, with 5 years of experience

Ideal Qualifications

  • Expertise in memory system (DDR, LPDDR, GDDR, HBM) and memory controller design
  • Experience working with Analog/Mixed-Signal circuits and PHYs
  • Experience with analog circuit modeling and writing SystemVerilog assertions
  • Knowledge of UPF and power-aware designs
  • MS/PhD EE or equivalent, with 7 years of experience

Top Skills

Systemverilog
Verilog
The Company
Santa Clara, California
49 Employees
On-site Workplace

What We Do

Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future

Jobs at Similar Companies

Alliant Credit Union Logo Alliant Credit Union

Data Analyst - Hybrid

Fintech • Financial Services
Hybrid
Chicago, IL, USA
843 Employees
Easy Apply
Remote
United States
985 Employees
Hybrid
Chicago, IL, USA
843 Employees

AffiniPay Logo AffiniPay

Sales Operations Manager

Fintech • Legal Tech • Payments • Sales • Software
Remote
United States
519 Employees

Similar Companies Hiring

Snyk Thumbnail
Software • Security • Information Technology • Data Privacy • Cybersecurity • Cloud • Artificial Intelligence
Boston, MA
1000 Employees
Consensus Cloud Solutions Thumbnail
Software • Information Technology • Healthtech • Cloud • Business Intelligence • Artificial Intelligence
Los Angeles, CA
398 Employees

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account